1. Field of Invention
This invention relates to data processing systems. More particularly, the invention relates to data processing systems having input/output drivers with reduced power consumption and noise levels.
2. Description of the Prior Art
In data processing systems using CMOS technology, power consumption and noise generation are dominated by switching circuit nodes. Input/output pins cause even greater power and noise disturbances during switching because of the amount of current required to charge the external buses capacitances. In such systems, memory buses and system input/output (I/O) buses are typically clocked with central processing unit (CPU) clock cycles at some multiple of one external bus clock cycle because external buses cannot be switched as quickly as the internal circuits of the CPU. For example, the ratio of CPU to external bus clock cycles may be 2 to 1, 3 to 1, 4 to 1, 3 to 2, etc. Because of the large number of I/O pins utilized for the buses, a power surge occurs with accompanying noise when the bus drivers for the memory and system I/O simultaneously change value.
Prior art attempts to control the effects of the power surge and noise in integrated circuits include the following:
U.S. Pat. No. 4,587,445 issued May 6, 1986, discloses a data output circuit capable of reducing the level of noise voltage generated through the power source line when the logic data are updated. The data output circuit includes means for preventing more than half the output lines from transitioning simultaneously.
U.S. Pat. No. 4,613,771 issued Sep. 23, 1986, discloses an integrated circuit having improved noise immunity. The circuit includes three power busses in the circuit, the busses being parasitically coupled in the substrate with proportioned parasitic resistive and capacitive coupling to reduce output noise.
U.S. Pat. No. 4,656,370 discloses an integrated circuit with divided power supply wiring which can practically avoid noise problems due to induced counter electromotive force of power supply and ground lines. Since the power supply and ground lines in the circuit are divided into plural sets and each set is provided with independent wirings, the magnitude of current change in each wiring and the value of each wiring inductance can be small. From this, switching noises caused by simultaneous similar data changes can be suppressed thereby avoiding erroneous operation.
U.S. Pat. No. 4,661,928 issued Apr. 28, 1987, discloses an output buffer in which inductive noise is suppressed without making the data output speed slow. An inductive noise at the voltage terminal for the output circuit is suppressed by providing a noise suppression signal between the output voltage terminal and the gate of the output transistor.
U.S. Pat. No. 4,724,340 issued Feb. 8, 1988 discloses an output circuit in which a switching noise is reduce by presetting pairs of output lines to opposite logic states. A first output signal is provided at a first output terminal in one of two possible logic states in response to a control signal. A second output signal on a second output terminal is at one of two possible logic states and responds to the control signal. A predispositioned circuit coupled to the first and second outputs causes the outputs to be at different logic states at least immediately prior to the first and second output signals appearing on the first and second output terminals.
U.S. Pat. No. 4,725,747 issued Feb. 16, 1988, discloses an integrated circuit which substantially eliminates or reduces the disadvantages and problems associated with switching noise and high-speed integrated circuits. A circuit includes a substrate having a plurality of transistor regions and an elongated gate having a predetermined resistance. A signal applied to one end of the gate propagates along the length of the gate during a predetermined time interval. The transistor regions sequentially conduct a response to the signal propagating along the elongated gate until all of the transistor regions are conductive. The sequential conduction of the transistor region reduces the generation of output noise by eliminating the change of output current with respect to time.
U.S. Pat. No. 4,857,765 issued Aug. 15, 1989, discloses a noise control system in an integrated circuit chip which controls noise by dividing drivers into groups and switching each group at different times. Time driver gating signals are used in conjunction with physical grouping of driver circuits on the chip to isolate switching drivers from quiet drivers. The grouping of drivers minimizes detrimental effects usually caused by noise that is generated when driver circuits switch.
A Japanese publication 59-148426, published Aug. 25, 1984, discloses a circuit for controlling timing of simultaneous operations to control noise.
A Japanese publication JP60-130920, published Jul. 12, 1985, discloses an integrated logic circuit which prevents the noise margin and reliability from being decreased by connecting each one of a plurality of capacitors where at least one capacitor has differing capacitances from the other capacitors at the other output logical gates.
While the prior art addresses problems of noise and power surges in integrated circuits, none of the art discloses controlling system elements in a data processing system to reduce noises and power surges at the pin I/O's of the system. Controlling the system elements of a data processing system in lieu of special circuits and devices would improve the performance of such data processing systems without the expense of added cost.